1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a refresh period detecting device for a semiconductor device that can automatically detect the refresh period according to system environments and a method of detecting the refresh period of the semiconductor memory device and a refresh period output device.
2. Description of the Prior Art
Generally, a dynamic random access memory (DRAM) uses a capacitor as a unit storage device into which data is written, and this is a cell. When writing data of 1 (or high) into the cell, a high voltage is applied thereto while a low voltage is applied thereto when writing data of 0 (or low) into the cell. It is preferable that the charge of a capacitor should be constant unless the voltage of its connecting terminal is changed. However, actually, the leakage current problem is caused as time goes by, and it cannot tell whether the stored data is 1 or 0. Accordingly, in order to maintain the storage data, the data stored in the cell must be periodically sensed and amplified, and then restored in that cell, which is referred to as refresh. Refresh for DRAM has several performance methods: RAS (row address strobe) only refresh and CAS before RAS refresh. In RAS only refresh, a row address strobe (/RAS) signal and a row address for performing refresh are applied to raise the voltage of a word line selected by the row address, and after data stored in all the cells connected to this word line is amplified by a sense amplifier and rewritten, the voltage of the word line then falls, which forms a single refresh cycle. According to this refresh, it is inconvenient to input all the corresponding row addresses from the outside in order to refresh all the cells of DRAMs.
CBR refresh (CAS before RAS refresh or auto-refresh) can solve this inconvenience. This CBR refresh is similar to RAS only refresh in the internal performance of sensing-amplification-restoring, and corresponding row addresses are internally generated in order without inputting row addresses from the outside. Accordingly, a user of DRAM does not have to memorize and input row addresses needing refresh. There is also a hidden refresh similar to CBR refresh. According to this hidden refresh, a refresh is performed in hiding as if it seems that refresh is not performed when viewed from the outside while column address strobe (/CAS) signal is active, /RAS signal is toggled, thus performing CBR refresh.
In a system using DRAM, DRAM just waits without doing anything in case that there is no need to use DRAM for a given period of time. In this case, refresh is required. Even if any command is input from the outside, time is calculated in DRAM to perform refresh in a required period of time, which is self-refresh.
Such refresh should be performed before the leakage current occurs to make it impossible to discriminate data, and this is a refresh period. Refresh is essential for DRAM but increases power consumption and interrupts the normal operation, which is not good for a user.
Therefore, much research and development are devoted to an increase in the refresh period in which the data can be maintained in the cell. A standard of the operating time in performing refresh of DRAM for a system is a refresh interval. The refresh interval is a value obtained by dividing the refresh period by the member of refresh cycle (the number of RAS cycle) for refresh the overall cells. The refresh interval is the maximum time interval by which a user gives a refresh command to refresh the DRAM.
As the refresh interval of DRAM 15.6 .mu.sec has been standardized since 2 msec/128 cycle (the number obtained by dividing the refresh period of 2 msec by 128 cycles , about 15.6 .mu.sec) was used in 16K-bit DRAM. The time interval of 7.8 .mu.sec becomes standardized in 256M-bit DRAM. A system using DRAM performs refresh once every minimum refresh intervals to prevent data from decaying. It is very important for DRAM to make the refresh period, the minimum value of time for refreshing all the cells, long. This time is closely related to the data retention time, a period of time for which data is stored in a cell and is not damaged. A principal cause of decaying data stored in a cell is the leakage current problem. This leakage current flows through a p-n junction or channel of a transistor (referred to as a cell transistor or an access transistor), serving as a switching device connecting the cell data storage terminal with a bit line. Such a current varies with the operating voltage and temperature, and is particularly changed by two times in response to a 10-degree variation of the operating temperature. The data retention time of DRAM significantly varies with the temperature and operating voltage. The refresh period is determined by data retention time under the worst operating condition in order to prevent data from decaying under the worst condition wherein DRAM operates. However, refresh is performed even though the data is safely kept in an actual system that does not use DRAM under the worst condition all the time, thus increasing the power consumption and a period of the time for which the DRAM does not perform its normal operation.
Manufacturing DRAMs of various standards by controlling the refresh period in response to the various system operating environment causes disadvantageous efficiency aspect of mass production and mass sale of DRAMs. There was a conventional technique of changing the refresh period by sensing the temperature and operating the refresh, taking the great variation of the leakage current with the temperature into consideration. However, it is difficult to exactly detect the temperature through a conventional DRAM process, and the temperature resolution is significantly decreased because of the variation in the process and problems in the circuitry thereby hardly expecting a satisfactory result.